Nearly 800 attended the virtual conference and exhibition
GAINESVILLE, Fla., March 08, 2022 (GLOBE NEWSWIRE) -- The 2022 virtual Design and Verification Conference and Exhibition U.S. (DVCon U.S.), sponsored by Accellera Systems Initiative (Accellera), concluded its 34th annual event last week. The 2022 Stuart Sutherland Best Paper and Poster winners, as voted on by attendees, were announced during a presentation at the close of day three of the program on Wednesday, March 2.
Overall attendance for DVCon U.S., including the free keynote, panel, UVM Birds-of-a-Feather and exhibit attendees, as well as all-access technical conference attendees, was close to 800.
“I’d like to thank everyone who participated in our 2022 virtual conference: our attendees and presenters, Conference Catalysts, Accellera and our committee members,” stated Vanessa Cooper, DVCon U.S. General Chair. “The steering committee did an outstanding job putting together an informative technical program and interactive exhibition for our attendees. We also had participation from the academic community this year, with students engaged and learning from practicing engineers. Networking continues to be an important element of DVCon and the addition of Gather.Town provided a unique platform to help facilitate face-to-face interaction among exhibitors and colleagues. I’d also like to congratulate our paper and poster winners for their excellent presentations. We look forward to seeing everyone in person next year for DVCon 2023!”
Awards for the Stuart Sutherland Best Paper Presentation:
1st Place “Systematic Constraint Relaxation (SCR): Hunting for over-constrained Stimulus”
- Authors: Debarshi Chatterjee, Spandan Kachhadiya, Ismet Bayraktaroglu, Siddhanth Dhodhi, Nvidia Corporation
2nd Place “Fnob: Command Line-Dynamic Random Generator”
- Authors: Haoxiang Hu, Facebook, Inc.; Tuo Wang, Facebook, Inc.
3rd Place “What Does the Sequence Say? Powering Productivity with Polymorphism”
- Author: Rich Edelman, Siemens EDA
Awards for Best Poster Presentation:
1st Place “Novel GUI Based UVM Test Bench Template Builder”
- Author: Vignesh Manoharan, Aeva
2nd Place “Why not “Connect” using UVM Connect: Mixed Language-communication got easier with UVMC”
- Author: Vishal Baskar, Siemens Industry Software Inc – Siemens EDA
3rd Place “A Low Maintenance Infrastructure to Jumpstart CPU Regression and Performance Correlation”
- Authors: Thomas Soong, Intel; Chenhui Huang, Intel; Christopher Browne, Intel
“Congratulations to all of our paper and poster winners this year,” stated John Dickol, DVCon U.S. Technical Program Committee Chair. “The highly technical presentations were excellent and many of them provided an opportunity for questions and interaction from the audience. One of the benefits of a virtual conference is that registered attendees can watch the recordings of the winning presentations, or any other session of interest, on-demand through March. I’d like to thank the Technical Program Committee for all their hard work over many months putting together a program we are all very proud of, and that attendees can learn from and apply to their projects.”
Highlights of the Week:
- Attendees had 42 papers, five tutorials, 14 posters, two panels, 10 short workshops, a UVM Birds of a Feather, a keynote, and an exhibition to explore throughout the four-day virtual program.
- Gather.Town was added this year to give attendees more opportunities to interact with presenters and colleagues in a more natural way. The game-like atmosphere provided areas to talk with peers either privately or in groups using video conferencing technology. The coffee breaks and exhibition took place on the Gather.Town platform.
- Manish Pandey, Vice President of Engineering, Synopsys, presented the keynote “Unleashing AI/ML for Faster Verification Closure” on Tuesday to an audience of approximately 200. He discussed advances in Machine Learning and how applying ML has enabled significant closure convergence and verification cycle reduction. His presentation was followed by a lively Q&A session moderated by DVCon U.S. General Chair Vanessa Cooper.
- Two intriguing panels were held on Wednesday. The first panel, “The Meeting of the SoC Verification Hidden Dragons,” moderated by Brian Bailey, Semiconductor Engineering, took a deep dive into finding and eliminating bugs during SoC verification. The second panel, “Going Faster – How to Cope with Shrinking Schedules and Increasing Complexity,” moderated by Eric Decker, Mythic, focused on the difficulty engineers face predicting schedules and trying to anticipate unforeseen challenges.
- A special registration rate for university students was added this year to encourage the academic community to connect with practicing engineers. Several students took advantage of the $39 registration fee, participating in the full conference program.
The recorded conference sessions are available for all-access registered attendees to view through March 31, 2022.
Save the date: DVCon U.S. 2023 will be held February 27 – March 2, 2023, at the DoubleTree Hotel in San Jose, California.
About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit www.dvcon.org. Follow DVCon on Facebook https://www.facebook.com/DvCon, LinkedIn or @dvcon_us on Twitter or to comment, please use #dvcon_us.
| For more information, please contact: | |
| Laura LeBlanc | Barbara Benjamin |
| Conference Catalysts, LLC | HighPointe Communications |
| 352-872-5544 Ext. 115 | 503-209-2323 |
| lleblanc@conferencecatalysts.com | barbara@hipcom.com |
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